Programmable memories have been implemented using non-volatile memory (NVM) cells, including split-gate NVM cells. These programmable memories can be implemented as stand-alone memory integrated circuits or can be embedded within other integrated circuits, as desired.
During operation, data stored within NVM cells can include errors. As such, many NVM systems use error correction code (ECC) routines to improve performance. For example, for multi-bit data located at a given address within the NVM system, an ECC routine is applied to the multi-bit data to generate ECC data that is stored within the NVM system along with the multi-bit data. When this multi-bit data is subsequently read from the address location, the ECC routine is performed again to re-generate the ECC data for the multi-bit data. The re-generated ECC data is then compared to the original ECC data to determine if there are single-bit, double-bit, or larger multi-bit errors within the multi-bit data read from the address location, depending upon the ECC routine applied to the multi-bit data. In particular, ECC routines are often employed that can identify, and correct single-bit errors, and that can identify, but not correct, double-bit errors.
As an NVM system is used over-time, the performance of NVM cells can degrade. This degradation in performance can increase the number of bit errors that occur when data is stored within the NVM system and when data is read from the NVM system. For some applications, this increase in bit errors can cause the NVM system to no longer have adequate reliability, thereby limiting the useful life of the NVM system for such applications.